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preliminary rev. 0.16 6/10 copyright ? 2008 by silicon laboratories si5334 this information applies to a product under dev elopment. its characteristics and specifications are s ubject to change without n otice. si5334 p in -c ontrolled a ny -f requency , a ny -o utput q uad c lock g enerator features applications description the si5334 is a high performance, low jitter clock generator capable of synthesizing any frequency on each of the device's four differential output clocks. the device accepts an external reference clock or crystal and generates four differential clock outputs, each of which is independently configurable to any frequency up to 350 mhz and select frequencies to 710 mhz. using silicon labs' patented multisynth technology, each output clock is generated with very low jitter and zero ppm frequency error. to provide additional design flexibility, each output clock is independently configurable to support any signal format and reference voltage. the si5334 provides low jitter frequency synthesis with outstanding frequency flexibility in a space-saving 4 x 4 mm qfn package. the device configuration is factory or field programmed and, upon power up, the device will begin operation in the predefined configuration without user intervention. the device supports operation from a 1.8, 2.5, or 3.3 v core supply. ? low-power multisynth technology enables independent, any-frequency synthesis on four differential output drivers ? highly-configurable output drivers support up to four differential outputs or eight single-ended clock outputs or a combination of both ? low phase jitter: 0.7 ps rms typ ? high-precision synthesis allows true 0 ppm frequency accuracy on all outputs ? flexible input reference ?? external crystal: 8 to 30 mhz ?? cmos input: 5 to 200 mhz ?? sstl/hstl input: 5 to 350 mhz ?? differential input: 5 to 710 mhz ? independently-configurable outputs support any frequency or format ?? lvpecl/lvds: 0.16 to 710 mhz ?? hcsl: 0.16 to 250 mhz ?? cmos: 0.16 to 200 mhz ?? sstl/hstl: 0.16 to 350 mhz ? independent output voltage per driver ?? 1.5, 1.8, 2.5, or 3.3 v ? independent core supply voltage ?? 1.8, 2.5, or 3.3 v ? frequency increment/decrement feature enables glitchless frequency adjustments in 1 ppm steps ? phase adjustment on each of the output drivers with <20 ps steps ? ssc on any or all outputs that is compliant to pci express ? optional external feedback mode allows zero-delay implementation ? loss-of-lock and loss-of-signal alarm ? simple pin control ? small size: 4x4 mm, 24-qfn ? low power: 45 ma core supply typ ? wide temperature range: ?40 to +85 c ? contact silicon labs for custom versions ? ethernet switch/router ? pci express 2.0/3.0 ? broadcast video/audio timing ? processor and fpga clocking ? any-frequency clock conversion ? msan/dslam/pon ? fibre channel, san ? telecom line cards ordering information: see page 24. pin assignments in1 clk2b clk2a vddo2 vddo1 clk1b clk1a vdd in6 in5 in4 in3 in2 vdd in7 clk3a clk3b loslol oeb vddo0 clk0b clk0a rsvd_gnd vddo3 gnd si5334 transparent top view
si5334 2 preliminary rev. 0.16 functional block diagram phase frequency detector loop filter vco clk0a p2 vddo1 vddo2 vddo3 vddo0 multisynth m0 pdec/fdec pinc/finc clk0b clk1a clk1b clk2a clk2b clk3a clk3b p1 in3 in2 in1 r1 multisynth m1 multisynth m2 multisynth m3 in6 in4 in5 osc multisynth n control nvm (otp) r0 r2 r3 input stage synthesis stage 1 (pll) synthesis stage 2 output stage control & memory oeb loslol vdd ref fb ram sspb refclkse fdbkse xtal/clkin fdbk xtal/clkinb fdbkb
si5334 preliminary rev. 0.16 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 2.2. crystal/clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3. zero delay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4. breakthrough multisynth technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5. output driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.6. output clock initial phas e offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.7. output clock phase increment a nd decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.8. output clock frequency increm ent and decrement . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.9. r divider consi derations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.10. spread spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.11. device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 2.12. loslol pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.13. power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.14. factory programming opti ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3. pin descriptions?si5334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4. device pinout by part number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 5. package outline: 24-lead qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6. recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. ordering information and standard frequency plans . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7.2. standard frequency plans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
si5334 4 preliminary rev. 0.16 1. electrical specifications table 1. recommended operating conditions (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit ambient temperature t a ?40 25 85 c core supply voltage v dd 2.97 3.3 3.63 v 2.25 2.5 2.75 v 1.71 1.8 1.98 v output buffer supply voltage v ddon 1.4 ? 3.63 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at nominal supply voltages and an operating temperature of 25 c unless otherwise noted. table 2. absolute maximum ratings parameter symbol test condition value unit dc supply voltage v dd ?0.5 to 3.8 v storage temperature range t stg ?55 to 150 c esd tolerance hbm (100 pf, 1.5 k ? ) 2.5 kv esd tolerance cdm 550 v esd tolerance mm 175 v latch-up tolerance jesd78 compliant junction temperature t j 150 c note: permanent device damage may occur if the absolute maxi mum ratings are exceeded. functional operation should be restricted to the conditions as specifi ed in the operational sections of this dat a sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
si5334 preliminary rev. 0.16 5 table 3. dc characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max unit core supply current i dd 100 mhz on all outputs, 25 mhz refclk ?4560 ma output buffer supply current i ddox lvpecl, 710 mhz ? ? 30 ma lvds, 710 mhz ? ? 8 ma hcsl, 250 mhz 2 pf load ??20 ma sstl, 350 mhz ? ? 19 ma cmos, 50 mhz 15 pf load ??28 ma cmos, 200 mhz 2 pf load, 3.3 v vdd0 ??20 ma cmos, 200 mhz 2 pf load, 2.5 v ?1317 ma cmos, 200 mhz 2 pf load, 1.8 v ?1115 ma hstl, 350 mhz ? ? 19 ma table 4. thermal characteristics parameter symbol test condition value unit thermal resistance junction to ambient ? ja still air 37 c/w thermal resistance junction to case ? jc still air 25 c/w table 5. performance characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test co ndition min typ max unit pll acquisition time t acq ??25 ms pll lock range f lock 5000 ? ? ppm pll loop bandwidth f bw ?1.6? mhz notes: 1. outputs at integer-related frequencie s and using the same driver format. 2. keep multisynth output frequency between 5 mhz to fvco/8. 3. only multisynth0 can have frequ ency inc/dec but multisynth0 c an be routed to any output. 4. spread spectrum is only available on clock outputs t hat are at 100 mhz and have the rn divider set to 1.
si5334 6 preliminary rev. 0.16 multisynth frequency synthesis resolution f res output frequency < fvco/8 0 0 1 ppb clkin loss of signal assert time t los ?2.6 5 s clkin loss of signal de-assert time t los_b 0.01 0.2 1 s pll loss of lock detect time t lol ?510 ms por to output clock valid t rdy ?? 2 ms input-to-output propagation delay t prop buffer mode (pll bypass) ?2.5? ns output-output skew t dskew rn divider = 1 1 ??100 ps programmable initial phase offset p offset ?45 ? +45 ns phase increment/decrement accuracy p step ??20 ps phase increment/decrement range p range ?45 ? +45 ns frequency range for phase increment/decrement f prange ? ? 350 2 mhz phase increment/decrement update rate p update pin control ? ? 1500 khz frequency increment/ decrement step size f step r divider not used 3 1 ? see note 2 ppm frequency increment/ decrement range f range r divider not used 3 ? ? 350 2 mhz frequency increment/ decrement update rate f update pin control 2,3 ? ? 1500 khz spread spectrum pp frequency deviation ss dev clock frequency of 100 mhz 4 ??0.5? % spread spectrum modulation rate ss dev clock frequency of 100 mhz 30 ? 33 khz table 5. performance characteristics (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test co ndition min typ max unit notes: 1. outputs at integer-related frequencie s and using the same driver format. 2. keep multisynth output frequency between 5 mhz to fvco/8. 3. only multisynth0 can have frequ ency inc/dec but multisynth0 c an be routed to any output. 4. spread spectrum is only available on clock outputs t hat are at 100 mhz and have the rn divider set to 1.
si5334 preliminary rev. 0.16 7 table 6. input and output clock characteristics (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units input clock (ac coupled differential input clocks on pins in1/2, in5/6) frequency f in 5 ? 710 mhz differential voltage swing v pp 710 mhz input 0.4 ? 2.4 v pp rise/fall time t r /t f 20%?80% ? ? 1.0 ns duty cycle 1 dc < 1 ns tr/tf 40 ? 60 % input impedance r in 10 ? ? k ? input capacitance c in ?3.5?pf input clock (dc-coupled single-e nded input clock on pins in3/4) frequency f in cmos 5 ? 200 mhz input voltage v i ?0.1 ? 3.63 vpp input voltage swing 200 mhz 0.8 ? 3.73 v rise/fall time t r /t f 20%?80% ? ? 2 ns duty cycle 2 dc < 2 ns tr/tf 40 ? 60 % input capacitance c in ?2.0?pf output clocks (differential) frequency 3 f out lvpecl, lvds 0.16 ? 350 mhz 367 ? 466 mhz 550 ? 710 mhz hcsl 0.16 ? 250 mhz lvpecl output voltage v oc common mode ? v ddo ? 1.4 v ?v v sepp peak-to-peak single- ended swing 0.55 0.8 0.96 v pp lvds output voltage (2.5/3.3 v) v oc common mode 1.125 1.2 1.275 v v sepp peak-to-peak single- ended swing 0.25 0.35 0.45 v pp lvds output voltage (1.8 v) v oc common mode 0.8 0.875 0.95 v v sepp peak-to-peak single- ended swing 0.25 0.35 0.45 v pp notes: 1. for best jitter performance, keep the input sl ew rate on in1/2, in5/6 faster than 0.3 v/ns. 2. for best jitter performance, keep the input single end ed slew rate on pins 3 or 4 faster than 1 v/ns. 3. only two unique frequencies above fvco/8 can be simultaneously output, fvco/4 and fvco/6. 4. includes effect of internal series 22 ? resistor.
si5334 8 preliminary rev. 0.16 hcsl output voltage v oc common mode 0.35 0.375 0.400 v v sepp peak-to-peak single- ended swing 0.575 0.725 0.85 v pp rise/fall time t r /t f 20%?80% ? ? 450 ps duty cycle dc 45 ? 55 % output clocks (single-ended) frequency f out cmos 0.16 ? 200 mhz sstl, hstl 0.16 ? 350 mhz cmos 20%?80% rise/fall time t r /t f 2 pf load ? 0.45 0.85 ns cmos 20%?80% rise/fall time t r /t f 15 pf load ? ? 1.7 ns cmos output resistance see note 4 ?50? ? sstl output resistance ?50? ? hstl output resistance ?50? ? cmos output voltage 4 v oh 4 ma load vddo ? 0.3 ? v v ol 4ma load ? 0.3 v sstl output voltage v oh sstl-3 vddox = 2.97 to 3.63 v 0.45xvddo+0.4 1 ??v v ol ?? 0.45xvddo? 0.41 v v oh sstl-2 vddox = 2.25 to 2.75 v 0.5xvddo+0.41 ? ? v v ol ?? 0.5xvddo? 0.41 v v oh sstl-18 vddox = 1.71 to 1.98 v 0.5xvddo+0.34 ? v v ol ?? 0.5xvddo? 0.34 v hstl output voltage v oh vddo = 1.4 to 1.6 v 0.5xvddo+0.3 ? ? v v ol ? ? 0.5xvddo ?0.3 v duty cycle dc 45 ? 55 % table 6. input and output clock characteristics (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test condition min typ max units notes: 1. for best jitter performance, keep the input sl ew rate on in1/2, in5/6 faster than 0.3 v/ns. 2. for best jitter performance, keep the input single end ed slew rate on pins 3 or 4 faster than 1 v/ns. 3. only two unique frequencies above fvco/8 can be simultaneously output, fvco/4 and fvco/6. 4. includes effect of internal series 22 ? resistor.
si5334 preliminary rev. 0.16 9 table 7. control pins (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol condition min typ max unit input control pins (in3, in4) input voltage low v il ?0.1 0.3 x vdd v input voltage high v ih 0.7 x vdd ?3.63 v input capacitance c in ?? 4 pf input resistance r in ?20?k ? output control pins (loslol) output voltage low v ol i sink =3ma ? 0 0.4 v rise/fall time 20?80% t r /t f c l < 10 pf, pull up ?? 1k ? ? ? 10 ns table 8. crystal specifications for 8 to 11 mhz parameter symbol min typ max unit crystal frequency f xtal 8?11mhz load capacitance (on-chip differential) c l 11 12 13 pf crystal output capacitance c o ?? 6 pf equivalent series resistance r esr ??300 ? crystal max drive level d l 100 ? ? w table 9. crystal specifications for 11 to 19 mhz parameter symbol min typ max unit crystal frequency f xtal 11 ? 19 mhz load capacitance (on-chip differential) c l 11 12 13 pf crystal output capacitance c o ?? 5 pf equivalent series resistance r esr ??200 ? crystal max drive level d l 100 ? ? w
si5334 10 preliminary rev. 0.16 table 10. crystal specifications for 19 to 26 mhz parameter symbol min typ max unit crystal frequency f xtal 19 26 mhz load capacitance (on-chip differential) c l 11 12 13 pf crystal output capacitance c o 5pf equivalent series resistance r esr 100 ? crystal max drive level d l 100 w table 11. crystal specifications for 26 to 30 mhz parameter symbol min typ max unit crystal frequency f xtal 26 30 mhz load capacitance (on-chip differential) c l 11 12 13 pf crystal output capacitance c o 5pf equivalent series resistance r esr 75 ? crystal max drive level d l 100 w table 12. jitter specifications 1,2 (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test c ondition min typ max unit gbe random jitter (12khz?20mhz) 3 j gbe clkin = 25 mhz all clkn at 125 mhz 4 ? 0.7 1 ps rms gbe random jitter (1.875?20 mhz) r jgbe clkin = 25 mhz all clkn at 125 mhz 4 ? 0.38 0.79 ps rms oc-12 random jitter (12 khz?5 mhz) j oc12 clkin = 19.44 mhz all clkn at 155.52 mhz 4 ? 0.7 1 ps rms pci express 3.0 random jitter (1.5 mhz?50 mhz) 3 j pcierj1 clkin = 25 mhz all clkn at 100 mhz spread spectrum not enabled 4 ? 0.6 1 ps rms notes: 1. all jitter measurements apply for lvds/hcsl/lvpecl output fo rmat with a low noise differential input clock and are made with an agilent 90804 oscilloscope. all rj measurements use rj/dj separation. 2. for best jitter performance, keep the single ended clock inpu t slew rates at pins 3 and 4 more than 1.0 v/ns and the differential clock input slew rates more than 0.3 v/ns. 3. d j for pci and gbe is < 5 ps pp 4. output multisynth in integer mode. 5. input frequency to the phase detector betw een 25 and 40 mhz and any output frequency > 5mhz. 6. measured in accordance with jedec standard 65. 7. rj is multiplied by 14; estimate the pp jitter from rj over 2 12 rising edges.
si5334 preliminary rev. 0.16 11 pci express 3.0 random jitter (12khz?20mhz) 3 j pcierj2 clkin = 25 mhz all clkn at 100 mhz spread spectrum not enabled 4 ? 0.7 1 ps rms pci express 3.0 period jitter clkin = 25 mhz all clkn at 100 mhz spread spectrum not enabled 4 ?815ps pk-pk pci express 3.0 cycle-cycle jitter clkin = 25 mhz all clkn at 100 mhz spread spectrum not enabled 4 ? 13 30 ps pk-pk period jitter j per n = 10,000 cycles 5 ? 10 30 ps pk-pk cycle-cycle jitter j cc n = 10,000 cycles output multisynth operated in integer or fractional mode 5 ? 9 29 ps pk 6 random jitter (12khz?20mhz) r j output and feedback multisynth in integer or fractional mode 5 ? 0.7 1.5 ps rms deterministic jitter d j output multisynth operated in fractional mode 5 ?315ps pk-pk output multisynth operated in integer mode 5 ?210ps pk-pk total jitter (12khz?20mhz) t j =d j +14xr j (see note 7 ) output multisynth operated in fractional mode 5 ? 13 36 ps pk-pk output multisynth operated in integer mode 5 ? 12 20 ps pk-pk table 12. jitter specifications 1,2 (continued) (v dd = 1.8 v ?5% to +10%, 2.5 v 10%, or 3.3 v 10%, t a = ?40 to 85 c) parameter symbol test c ondition min typ max unit notes: 1. all jitter measurements apply for lvds/hcsl/lvpecl output fo rmat with a low noise differential input clock and are made with an agilent 90804 oscilloscope. all rj measurements use rj/dj separation. 2. for best jitter performance, keep the single ended clock inpu t slew rates at pins 3 and 4 more than 1.0 v/ns and the differential clock input slew rates more than 0.3 v/ns. 3. d j for pci and gbe is < 5 ps pp 4. output multisynth in integer mode. 5. input frequency to the phase detector betw een 25 and 40 mhz and any output frequency > 5mhz. 6. measured in accordance with jedec standard 65. 7. rj is multiplied by 14; estimate the pp jitter from rj over 2 12 rising edges.
si5334 12 preliminary rev. 0.16 table 13. typical phase noise performance offset frequency 25mhz xtal to 156.25 mhz 27 mhz ref in to 148.3517 mhz 19.44 mhz ref in to 155.52 mhz units 100 hz ?90 ?87 ?110 dbc/hz 1 khz ?120 ?117 ?116 10 khz ?126 ?123 ?123 100 khz ?132 ?130 ?128 1 mhz ?132 ?132 ?128 10 mhz ?145 ?145 ?145
si5334 preliminary rev. 0.16 13 2. functional description 2.1. overview figure 1. si5334 block diagram the si5334 is a high-performance, low-jitter clock generator capable of synthesizing any frequency on each of the device's four di fferential output clocks. the device accepts an external crystal from 8 to 30 mhz or an input clock ranging from 5 to 710 mhz. each output is independently factory-programmable to any frequency up to fvco/8 (max of 350 mhz) and select frequencies to 710 mhz. the si5334 fractional-n pll, comprised of a phase detector, charge pump, loop filter, vco, and dividers, is fully integrated on chip to simplify design. using silicon labs' patented multisynth technology, each output clock is generated with low jitter and zero ppm frequency error. the device has four multisynth output dividers to provide non-integer frequency synthesis on every differential output clock. the si5334 output driver is highly flexible. the signal format of each output clock can be user-specified to support lvpecl, lvds, hcsl, cmos, hstl, or sstl. each output clock has its own supply voltage to allow for the utmost flexibility in mi xed supply operations. the core of the si5334 has its own supply voltage that can be 1.8, 2.5, or 3.3 v. the si5334 supports an optional zero delay mode of operation. in this mode, one of the device output clocks is fed back to the fdbk/fdbkb clock input pins to implement the pll feedback path and nullify the phase difference between the refe rence input and the output clocks. the si5334d/e/f has a pin- controlled phase increment/ decrement feature that allows the user to adjust the phase of each output clock in relation to the other output clocks. the phase of each differential output clock can be set to an accuracy of 20 ps over a range of 45 ns. this feature is available over the 0.16 to fvco/8 mhz frequency range at a maximum rate of phase change of 1.5 mhz. the si5334g/h/j has a pin-controlled frequency increment/decrement feature that allows the user to change frequency in steps as small as 1 ppm of the initial frequency to as large as possible as long as the frequency at the output of the multisynth stays within the range of 5 mhz to fvco/8 mhz. this feature is available on clk0a/b only. the frequency step is glitchless. this feature is useful in applications that require a variable clock frequency. it can also be used in frequency margining applicat ions to margin test system clocks during design/verific ation/test or manufacturing test applications. for emi reduction, the si 5334k/l/m supports pci express 2.0 compliant spread spectrum on all output clocks that are 100 mhz. phase frequency detector loop filter vco clk0a p2 vddo1 vddo2 vddo3 vddo0 multisynth m0 pdec/fdec pinc/finc clk0b clk1a clk1b clk2a clk2b clk3a clk3b p1 in3 in2 in1 r1 multisynth m1 multisynth m2 multisynth m3 in6 in4 in5 osc multisynth n control nvm (otp) r0 r2 r3 input stage synthesis stage 1 (pll) synthesis stage 2 output stage control & memory oeb loslol vdd ref fb ram sspb refclk1 fdbkse xtal/clkin fdbk xtal/clkinb fdbkb
si5334 14 preliminary rev. 0.16 the si5334 is pin-controlled. no i 2 c interface is provided. the lollos output pin indicates the lock condition of the pll. an output enable input pin is available on the si5334a/b/c which affects all the programmed clock outputs. all device specifications are guaranteed across these three core supply voltages. packaged in a rohs-6, pb-free 4x4 mm qfn package, the device supports the industrial temperature range of ?40 to +85 c. after core power is applied, the si5334 downloads the factory-programmed nvm into ram and begins operation. 2.2. crystal/clock input the device can be driven from either a low frequency fundamental mode crystal (8?30 mhz) or an external reference clock (5?710 mhz). the crystal is connected across pins in1 and in2. the pcb traces between the crystal and the device must be kept very short to minimize stray capacitance. to ensure maximum compatibility with crystals from multiple vendors, the internal crystal oscillator provides adaptive crystal drive strength based upon the crystal frequency. the crystal load capacitors are placed on-chip to reduce external component count. if a crystal with a load capacitance outside the range specified in tables 3?7 is supplied to the device , it will result in a slight ppm error in the device clock output frequencies. this error can be compensated for by a small change in the input to output multiplication ratio. if a reference clock is used, the device accepts a single- ended input reference on in3 or a differential lvpecl, lvds, or hcsl source on in1 and in2. the input at in3 can accept an input frequency up to 200 mhz. the signal applied at in3 should be dc-coupled because internally this signal is ac-coupled to the receive input. a single-ended reference clock up to 350 mhz can be ac- coupled to in1. a differential reference clock, such as lvpecl, lvds or hcsl, is input on in1,2 for frequencies up to 700 mhz. the differential input to in1,2 requires 0.1 f ac coupling caps to be located near the device and a 100 ? termination resistor to be located between these caps and the transmission line going back to the differential driver. see ?an408: termination options for any-frequency, any-output clock generators and clock buffers? for more information on connecting input signals to in1,2,3. this application note can be downloaded from www.silabs.com/timing . 2.3. zero delay mode a clock that is input to the si5334 will have an unspecified amount of delay from the input pins to the output pins. the zero delay mode can be used to reduce the delay through the si5334 to typically less than 100 ps. this is accomplished by feeding back the clk3 output to either in4 or in5,6. using clk3 allows for an easy pcb route of this signal back to the input. the r3 divider must be set to 1 when using feedback from clk3 to implement the zero delay mode. all output clocks that are required to have zero de lay must also have their rn divider set to 1. a single-ended signal up to 200 mhz from clk3 can be input to in4. a single- ended signal up to 350 mhz from clk3 can be input to in5 using the technique shown in an408. a differential signal up to 710 mhz from clk3a,b must be input to in5,in6. the in4 input is electrically the same as in3 described above. the in5,in6 inputs are electrically the same as the in1,in2 inputs described above. see an408 for additional information on signal connections for the zero delay mode. 2.4. breakthrough multisynth technology next-generation timing ic architectures require a wide range of frequencies which are often non-integer related. traditiona l clock architecture s address this by using multiple single pll ics, often at the expense of bom complexity and power. the si5334 and si5338 use patented multisynth technology to dramatically simplify timing architectures by integrating the frequency synthesis capability of 4 phase-locked loops (plls) in a single device, greatly minimizing size and power requirements versus traditional solutions. based on a fractional-n pll, the heart of the architecture is a low phase noise, high frequency vco. the vco supplies a high frequency output clock to the multisynth block on each of the four independent output paths. each multisynth operates as a high speed fractional divider with silicon labs' proprietary phase error correction to divide down the vco clock to the required output frequency with very low jitter. the first stage of the multisynth architecture is a fractional-n divider which switches seamlessly between the two closest integer divider values to produce the exact output clock frequency with 0 ppm error. to eliminate phase error generated by this process, multisynth calculates the relative phase difference between the clock produced by the fractional-n divider and the desired output clock and dynamically adjusts the phase to match the ideal clock waveform. this novel approach makes it possible to generate any output clock frequency without sacrificing jitter performance.
si5334 preliminary rev. 0.16 15 based on this architecture, the output of each multisynth can produce any frequency from 5 to fvco/8 mhz. to support higher frequency operation, the multisynth divider can be bypassed. in bypass mode integer divide ratios of 4 and 6 are supported, which allows for output frequencies of fvco/4 and fvco/6 mhz which translates to 367?473.3 mhz and 550?710 mhz respectively. because each multisynth uses the same vco output there are output frequency limitations when output frequencies greater than fvco/8 are desired. for example, if 375 mhz is needed at the output of multisynth0, the vco frequency would need to be 2.25 ghz. now, all the other multisynths can produce any frequency from 5 mhz up to a maximum frequency of 2250/8 = 281.25 mhz. multisynth1,2,3 could also produce fvco/4 = 562.5 mhz or fvco/6 = 375 mhz. only two unique frequencies above fvco/8 can be output: fvco/6 and fvco/4. 2.5. output driver there are four clock output channels on the si5334 (clk0,clk1,clk2,clk3) with two signal outputs per channel. each channel may be programmed to be a differential driver or a dual single ended driver. if a channel is factory-programmed to be single ended, then the two outputs for that channel can be factory- programmed to be in-phase or out-of-phase. si5334 output drivers can be configured as single ended cmos, sstl, hstl or differential lvpecl, lvds, and hcsl formats. the supply voltage requirement for each driver format is selectable as shown in table 14. all unused clock output channels must have their respective vdd0x supply voltage connected to pin 7 and 24 vdd. figure 2. silicon labs? multisynth technology fractional-n divider phase adjust phase error calculator divider select (div1, div2) f vco f out multisynth table 14. output driver signal format selection vdd0x supply voltage cmos sstl hstl lvpecl lvds hcsl 1.5 x 1.8 x x x x 2.5 x x x x x 3.3 x x x x x
si5334 16 preliminary rev. 0.16 an oeb pin is provided to enable/disable the output clocks. when oeb = 0, all outputs that have been factory programmed will be on. when oeb = 1, all clock outputs that have been fa ctory programmed will be off and held to a low level. 2.6. output clock initial phase offset each clkn output of the si5334 can have its own unique initial phase offset over a range of +- 45 ns with an accuracy of 20 ps. when the respective r divider is not set to 1, this function is not supported. 2.7. output clock phase increment and decrement the si5334d/e/f has a pin-controlled phase increment/ decrement feature that allows the user to adjust the phase of 1 or more output clocks via pin control. since their is only 1 pin for increment and 1 pin for decrement, each output clock channel needs to be enabled or disabled for this feature. in addition, the magnitude of the phase step must be set for each clock output channel. the phase adjustment accuracy is 20 ps over a range of 45 ns, and the phase transition is glitchless. this feature is not availabl e on any clock output that has spread spectrum enabled. the maximum clock output frequency supported in this mode of operation is fvco/ 8, where fvco is the frequency of the device's internal voltage controlled oscillator for the config ured frequency plan. the phase can be changed at a maximum rate of 1.5 mhz. in order to increment or decrement phase it is necessary to input a positive pulse of >100ns followed by a low of >100 ns. since this feature uses pins 3 and 4, the reference clock must be input at pins 1 and 2 or the crystal used across these pins. once a si5334/d/e/ f is factory-programmed, the phase increment/ decrement parameters cannot be changed. if one desires to subsequently change the phase increment/ decrement parameters on a factory-programmed part, the si5338 clock generator must be used. if a phase decrement causes a single multisynth clock period to be less than 8/fvco, all clock outputs may turn off for up to 10 clock periods and then come back on with the phase setting bef ore the illegal decrement. 2.8. output clock frequency increment and decrement the si5334g/h/j has a pin-controlled frequency increment/decrement feature that allows the user to adjust the frequency at the output of multisynth0 only. multisynth0 can be connected to any or all of the four output clock buffers with the muxes shown in the " functional block diagram" on page 2. if frequency increment and decrement is required on the other clock outputs the si5338 should be used. the magnitude of a single frequency step mu st be factory-programmed. spread spectrum and frequency increment/decrement cannot both be active on the same clock output. there is a single pin to control the frequency increment and a single pin to control the frequency decrement. the frequency increment or decrement step size can be factory-programmed from as low as 1 ppm of the initial frequency to a maximum that keeps the output of the multisynth within the limits of 5 mhz to fvco/8. if a frequency increment causes the multisynth0 output frequency to go above fvco/8, then all output clocks may turn off for up to 10 clock cycles and then come back on at the frequency before the increment. if the output frequency needs to go below 5 mhz, refer to "2.9. r divider consideratio ns" on page 16 for further information. the frequency transition is glitchless. the frequency can be changed at a maximum rate of 1.5 mhz. in order to increment or decrement frequency it is necessary to input a positive pulse of >100 ns followed by a low of > 100 n s. since this feature uses pins 3 and 4, the reference cl ock must be input at pins 1 and 2 or the crystal used across these pins. once a si5334/g/h/j is factory-programmed, the frequency increment/decrement parameters cannot be changed. if one desires to subsequently change the frequency increment/decrement parameters on a programmed part, the si5338 clock generator must be used. 2.9. r divider considerations when the requested output frequency of a channel is below 5 mhz, the rn (n = 0,1,2,3) divider will automatically be set and enabled. when the rn divider is active the step size range of the frequency increment and decrement func tion will decrease by the rn divide ratio. the rn divider can be set to {1, 2, 4, 8, 16, 32}. non-unity settings of r0 will affect the finc/fdec step size at the multisynth0 output. for example, if the multisynth0 output step size is 2.56 mhz and r0 = 8, the step size at the output of r0 will be 2.56 mhz divided by 8 = .32 mhz. when the rn divider is set to non-unity, the initial phase of the clkn output with respect to other clkn outputs is not guaranteed.
si5334 preliminary rev. 0.16 17 2.10. spread spectrum figure 3. spread spectrum triangle waveform to reduce the electromagnetic interference (emi), the si5334k/l/m supports pci express compliant spread spectrum on all outputs that are 100 mhz. if clk0 has spread spectrum enabled, then the finc/fdec function is not available on clk0. spread spectrum modulation spreads the energy across many frequencies to reduce the emi across a narrow range of frequencies. the modulation rate is the time required to transition from the maximum spread spectrum frequency to the minimum spread spectrum frequency and then back to the maximum frequency as shown in figure 3. the si5334k/l/m supports 0.5% downspread at a 30? 33 khz rate with a clock frequency of 100 mhz in compliance with the pci express standard. when pin 12 (sspb) is low the factor y-programmed clock outputs will have spread spec trum turned on. 2.11. device reset to reset the device, a powe r cycle must be performed. 2.12. loslol pin when either a loss of lock (lol) or loss of signal (los) condition occurs the loslol pin will assert. the los condition occurs when there is no input clock input to the si5334. the loss of lock algorithm works by continuously monitoring the frequency difference between the two inputs of t he phase frequency detector. when this frequency difference is greater than 1000 ppm, a loss of lock condition is declared. note that the vco will track the input clock frequency for up to ~50000 ppm, which will keep the inputs to the phase frequency detector at the same frequency until the pll comes out of lock. when a clock input is removed, the loslol pin will assert, and the clock outputs may drift up to 5%. when the input clock with an appropriate frequency is re-applied, the pll will again lock. 2.13. power-up upon powerup, the device performs an internal self- calibration before operation to optimize loop parameters and jitter performance. while the self-calibration is being performed, the device vco is being internally controlled by the self-calibration state machine and the lol alarm is masked. the ou tput clocks appear after the device finishes self calibration. 2.14. factory programming options silicon labs si5334 clock generators are factory- programmable devices. the functions and frequency plans can be customized to meet the needs of your applications. contact your local silicon labs sales representative. output clock frequency modulation rate time
si5334 18 preliminary rev. 0.16 3. pin descriptions?si5334 note: center pad must be tied to gnd for normal operation. table 15. si5334 pin descriptions pin # pin name i/o signal type description 1,2 in1/in2 i multi clkin/clkinb. these pins are used as the main differential clock input or as the xtal input. clock inputs to these pins must be ac-coupled. a crystal should be directly connected to pins 1,2 with the shortest traces possible. keep the traces from pins 1,2 to the crystal as short as possible and keep other signals and radiating sources away from the crystal. when not in use, leave in1 unconnected and in2 connected to gnd. in1 clk2b clk2a vddo2 vddo1 clk1b clk1a vdd in6 in5 in4 in3 in2 vdd in7 clk3a clk3b loslol oeb vddo0 clk0b clk0a rsvd_gnd vddo3 gnd gnd
si5334 preliminary rev. 0.16 19 3in3 imulti keep the input level > ?0.1 v and < v dd +.1 v. refclkse high impedance input for single-ended clock signals such as cmos. the input should be dc-coupled. pinc this pin function is active for devices si5334d/e/f. a positive pulse of greater than 100 ns width (followed by >100 ns low) will increase the input to output device latency by a factory-programmed amount. the function of this pin is factory programmed. finc this pin function is active for devices si5334g/h/j. a positive pulse of greater than 100 ns width (followed by >100 ns low) will increase th e output frequency of the clock output by a factory-programmed amount. the function of this pin is factory-programmed. if this pin is unused, it should be grounded. 4in4 ilvcmos keep the input level > ?0.1 v and < vdd+ 0.1 v. fdbkse high impedance input for single-ended clock signals, such as cmos, when the zero delay mode of operation is required. this input should be dc-coupled. pdec this pin function is active for devices si5334d/e/f. a positive pulse of greater than 100 ns width (followed by >100 ns low) will decrease the input to output device latency by a factory-programmed amount. the function of this pin is factory-programmed. fdec this pin function is active for devices si5334g/h/j. a positive pulse of greater than 100 ns width (followed by >100 ns low) will decrease the output frequency of the clock output by a factory-programmed amount. the function of this pin is factory-programmed. if this pin is unused, it should be grounded. 5,6 in5/in6 i multi fdbk/fdbkb these pins form a differential input for feedback clock signals when a zero delay mode of operation is in effect. always ac couple into these pins. when not is use leave fdbk unconnected and connect fdbk to ground. 7 vdd vdd supply core supply voltage the device operates from a 1. 8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located ve ry close to this pin. table 15. si5334 pin descriptions (continued) pin # pin name i/o signal type description
si5334 20 preliminary rev. 0.16 8 loslol o open drain loss of signal or loss of lock indicator. 0 = no los or lol condition. 1 = a los or lol condition has occurred. for this pin a 1?5 k ? pull-up resistor to a voltage is required. this voltage may be as high as 3.63 v regardless of the voltage on pin 7. 9 clk3b o multi output clock b for channel 3 may be a single-ended output or half of a differential out- put with clk3a being the other differential half. if unused leave this pin floating. 10 clk3a o multi output clock a for channel 3 may be a single-ended output or half of a differential output with clk3b being the other differential half. if unused leave this pin floating. 11 vddo3 vdd supply output clock supply voltage supply voltage (3.3, 2.5, 1.8, or 1.5 v) for clk3a,b. a 0.1 f capacitor must be located very close to this pin. if clk3 is not used, this pin must be tied to vdd (pin 7, 24). 12 in7 i supply sspb. when low, spread spectrum is enabled on every output clock that is programmed for spread spectrum. this option is available on the si5334k/l/m. on an si5334 that does not contain the spread spectrum functionality, this pin should be connected to gnd. 13 clk2b o multi output clock b for channel 2 may be a single-ended output or half of a differential output with clk2a being the other differential half. if unused leave this pin floating. 14 clk2a o multi output clock a for channel 2 may be a single-ended output or half of a differential output with clk2b being the other differential half. if unused leave this pin floating. 15 vddo2 vdd supply output clock supply voltage. supply voltage (3.3, 2.5, 1.8, or 1.5 v) for clk2a,b. a 0.1 f capacitor must be located very close to this pin. if clk2 is not used, this pin must be tied to vdd (pin 7, 24). 16 vddo1 vdd supply output clock supply voltage. supply voltage (3.3, 2.5, 1.8, or 1.5 v) for clk1a,b. a 0.1 f capacitor must be located very close to this pin. if clk1 is not used, this pin must be tied to vdd (pin 7, 24). table 15. si5334 pin descriptions (continued) pin # pin name i/o signal type description
si5334 preliminary rev. 0.16 21 17 clk1b o multi output clock b for channel 1 may be a single-ended output or half of a differential output with clk1a being the other differential half. if unused, this pin must be tied to vdd pin 24. if unused leave this pin floating. 18 clk1a o multi output clock a for channel 1 may be a single-ended output or half of a differential output with clk1b being the other differential half. if unused leave this pin floating. 19 oeb i lvcmos output enable low when low, all the factory-programmed outputs are enabled. when high all factory programmed outputs are forced to a logic low. 20 vddo0 vdd supply output clock supply voltage. supply voltage (3.3, 2.5, 1.8, or 1.5 v) for clk0a,b. a 0.1 f capacitor must be located very close to this pin. if clk0 is not used, this pin must be tied to vdd (pin 7, 24). 21 clk0b o multi output clock b for channel 0 may be a single-ended output or half of a differential output with clk0a being the other differential half. if unused leave this pin floating. 22 clk0a o multi output clock a for channel 0 may be a single-ended output or half of a differential output with clk0b being the other differential half. if unused leave this pin floating. 23 rsvd_gnd gnd gnd ground. must be connected to system ground. 24 vdd vdd supply core supply voltage. the device operates from a 1. 8, 2.5, or 3.3 v supply. a 0.1 f bypass capacitor should be located ve ry close to this pin. gnd pad gnd gnd gnd ground pad. this is the large pad in the center of the package. device specifications cannot be guaranteed unless the ground pad is properly connected to a ground plane on the pcb. see section 6.0 for the pcb pad sizes and ground via requirements. table 15. si5334 pin descriptions (continued) pin # pin name i/o signal type description
si5334 22 preliminary rev. 0.16 4. device pinout by part number the si5334 is orderable in three different speed gr ades: si5334a/d/g/k have a maxi mum output clock frequency limit of 710 mhz. si5338b/e/h/l have a maximum outpu t clock frequency of 350 mhz. si5338c/f/j/m have a maximum output clock frequency of 200 mhz. brief pin functions follow. ? xtal/clkin ?crystal or one side of differential input clock ? xtal/clkinb ?crystal or one side of differential input clock ? refclkse ?single-ended reference clock input ? fdbkse ?single-ended feedback clock input ? fdbk ?differential feedback input ? fdbkb ?differential feedback input inverted ? finc ?frequency increment pin ? fdec ?frequency decrement pin ? pinc ?phase increment pin ? pdec ?phase decrement pin ? oeb ?output enable low see the four groupings below for the available pin control functions on pins 3, 4 and 12. xtal/clkin clk2b clk2 vddo2 vddo1 clk1b clk1 vdd vdd gnd clk3 clk3b intr oeb vddo0 clk0b clk0 rsvd_gnd vddo3 si5334a-axxxxx-gm si5334b-axxxxx-gm si5334c-axxxxx-gm 1 2 3 4 5 6 789101112 13 14 15 16 17 18 19 20 21 22 23 24 refclkse fdbkse fdbk fdbkb xtal/clkinb xtal/clkin clk2b clk2 vddo2 vddo1 clk1b clk1 vdd vdd gnd clk3 clk3b intr oeb vddo0 clk0b clk0 rsvd_gnd vddo3 si5334d-axxxxx-gm si5334e-axxxxx-gm si5334f-axxxxx-gm 1 2 3 4 5 6 789101112 13 14 15 16 17 18 19 20 21 22 23 24 xtal/clkinb pinc pdec fdbk fdbkb pin # function pin # function pin # function pin # function 1 xtal/clkin 13 clk2b 1 xtal/clkin 13 clk2b 2 xtal/clkinb 14 clk2 2 xtal/clkinb 14 clk2 3 refclkse 15 vddo2 3 pinc 15 vddo2 4 fdbkse 16 vddo1 4 pdec 16 vddo1 5 fdbk 17 clk1b 5 fdbk 17 clk1b 6 fdbkb 18 clk1 6 fdbkb 18 clk1 7 vdd 19 oeb 7 vdd 19 oeb 8 intr 20 vddo0 8 intr 20 vddo0 9 clk3b 21 clk0b 9 clk3b 21 clk0b 10 clk3 22 clk0 10 clk3 22 clk0 11 vddo3 23 rsvdgnd 11 vddo3 23 rsvdgnd 12 gnd 24vdd 12 gnd 24vdd
si5334 preliminary rev. 0.16 23 xtal/clkin clk2b clk2 vddo2 vddo1 clk1b clk1 vdd vdd gnd clk3 clk3b intr oeb vddo0 clk0b clk0 rsvd_gnd vddo3 si5334g-axxxxx-gm si5334h-axxxxx-gm si5334j-axxxxx-gm 1 2 3 4 5 6 789101112 13 14 15 16 17 18 19 20 21 22 23 24 xtal/clkinb finc fdec fdbk fdbkb xtal/clkin clk2b clk2 vddo2 vddo1 clk1b clk1 vdd vdd sspb clk3 clk3b intr oeb vddo0 clk0b clk0 rsvd_gnd vddo3 si5334k-axxxxx-gm si5334l-axxxxx-gm si5334m-axxxxx-gm 1 2 3 4 5 6 789101112 13 14 15 16 17 18 19 20 21 22 23 24 xtal/clkinb refclkse fdbkse fdbk fdbkb pin # function pin # function pin # function pin # function 1 xtal/clkin 13 clk2b 1 xtal/clkin 13 clk2b 2 xtal/clkinb 14 clk2 2 xtal/clkinb 14 clk2 3 finc 15 vddo2 3 refclkse 15 vddo2 4 fdec 16 vddo1 4 fdbkse 16 vddo1 5 fdbk 17 clk1b 5 fdbk 17 clk1b 6 fdbkb 18 clk1 6 fdbkb 18 clk1 7 vdd 19 oeb 7 vdd 19 oeb 8 intr 20 vddo0 8 intr 20 vddo0 9 clk3b 21 clk0b 9 clk3b 21 clk0b 10 clk3 22 clk0 10 clk3 22 clk0 11 vddo3 23 rsvdgnd 11 vddo3 23 rsvdgnd 12 gnd 24 vdd 12 sspb 24 vdd
si5334 24 preliminary rev. 0.16 5. package outline: 24-lead qfn figure 4. 24-lead quad flat no-lead (qfn) table 16. package dimensions dimension min nom max a 0.80 0.85 0.90 a1 0.00 0.02 0.05 b 0.18 0.25 0.30 d4.00 bsc. d2 2.35 2.50 2.65 e0.50 bsc. e4.00 bsc. e2 2.35 2.50 2.65 l 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jede c outline mo-220, variation vggd-8. 4. recommended card reflow profile is per the jede c/ipc j-std-020c specification for small body components.
si5334 preliminary rev. 0.16 25 6. recommended pcb layout table 17. pcb land pattern dimension min nom max p1 2.50 2.55 2.60 p2 2.50 2.55 2.60 x1 0.20 0.25 0.30 y1 0.75 0.80 0.85 c1 3.90 c2 3.90 e0.50 notes: general 1. all dimensions shown are in millimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. connect the center ground pad to a ground plane with no less than five vias to a ground plane that is no more than 20 mils below it. via drill size should be no smaller than 10 mils. a longer distance to the ground plane is allowed if more vias are us ed to keep the inductance from increasing. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clea rance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 9. a 2x2 array of 1.0 mm square openings on 1.25 mm pitch should be used for the center ground pad. card assembly 10. a no-clean, type-3 solder paste is recommended. 11. the recommended card reflow profile is per the jedec/ip c j-std-020c specification for small body components.
si5334 26 preliminary rev. 0.16 7. ordering information an d standard frequency plans 7.1. ordering information si5334x si5334 pin-controlled clock generator product family axxxxx gmr 1 st option code: clock output frequency range a 0.16 mhz to 710 mhz b 0.16 mhz to 350 mhz c 0.16 mhz to 200 mhz d 0.16 mhz to 710 mhz phase inc/dec pin control e 0.16 mhz to 350 mhz phase inc/dec pin control f 0.16 mhz to 200 mhz phase inc/dec pin control g 0.16 mhz to 710 mhz freq inc/dec pin control h 0.16 mhz to 350 mhz freq inc/dec pin control j 0.16 mhz to 200 mhz freq inc/dec pin control k 0.16 mhz to 710 mhz ssc l 0.16 mhz to 350 mhz ssc m 0.16 mhz to 200 mhz ssc a = product revision a 2 nd option code = xxxxx a five-character code will be assigned for each unique configuration . device starts operation upon powerup. see table 10 for a listing of available configurations. to request a configuration not listed in the table, contact your silicon labs sales representative . certain restrictions apply. operating temp range: -40 to +85 c package: 4 x 4 mm qfn, rohs6, pb-free r = tape & reel (blank) = tubes
si5334 preliminary rev. 0.16 27 7.2. standard frequency plans table 18. si5334 standard frequency plans clkin clk0 clk1 clk2 clk3 application opn input freq format fre q format freq format freq format freq format sonet/sdh si5334c- a00099-gm clock 19.4400 3.3 v cmos 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl 77.7600 3.3 v lvpecl 77.7600 3.3 v lvpecl si5334c- a00101-gm clock 19.4400 3.3 v cmos 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl si5334a- a00102-gm clock 19.4400 3.3 v cmos 622.0800 3.3 v lvpecl 622.0800 3.3 v lvpecl 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl si5334c- a00103-gm clock 38.8800 3.3 v cmos 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl 77.7600 3.3 v lvpecl 77.7600 3.3 v lvpecl si5334c- a00104-gm clock 38.8800 3.3 v cmos 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl si5334a- a00105-gm clock 38.8800 3.3 v cmos 622.0800 3.3 v lvpecl 622.0800 3.3 v lvpecl 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl si5334c- a00106-gm clock 155.5200 3.3 v lvpecl 161.1328 3.3 v lvpecl 156.2500 3.3 v lvpecl 156.2500 3.3 v lvpecl 155.5200 3.3 v lvpecl ethernet/fibre channel si5334c- a00107-gm xtal 25.0000 n/a 161.1328 3.3 v lvpecl 156.2500 3.3 v lvpecl 125.0000 3.3 v lvpecl 25.0000 3.3 v cmos si5334c- a00108-gm clock 25.0000 3.3 v cmos 161.1328 3.3 v lvpecl 156.2500 3.3 v lvpecl 125.0000 3.3 v lvpecl 25.0000 3.3 v cmos si5334b- a00109-gm xtal 25.0000 n/a 312.5000 3.3 v lvpecl 156.2500 3.3 v lvpecl 125.0000 3.3 v lvpecl 62.5000 3.3 v cmos si5334b- a00110-gm clock 25.0000 3.3 v cmos 312.5000 3.3 v lvpecl 156.2500 3.3 v lvpecl 125.0000 3.3 v lvpecl 62.5000 3.3 v cmos si5334c- a00111-gm xtal 25.0000 n/a 125.0000 3.3 v cmos 125.0000 3.3 v cmos 125.0000 3.3 v cmos 125.0000 3.3 v cmos si5334c- a00112-gm clock 25.0000 3.3 v cmos 125.0000 3.3 v cmos 125.0000 3.3 v cmos 125.0000 3.3 v cmos 125.0000 3.3 v cmos si5334c- a00113-gm xtal 25.0000 n/a 125.0000 1.8 v lvds 125.0000 1.8 v lvds 125.0000 1.8 v lvds 125.0000 1.8 v lvds si5334c- a00114-gm clock 25.0000 3.3 v cmos 125.0000 1.8 v lvds 125.0000 1.8 v lvds 125.0000 1.8 v lvds 125.0000 1.8 v lvds si5334c- a00115-gm xtal 25.0000 n/a 156.2500 1.8 v lvds 156.2500 1.8 v lvds 125.0000 1.8 v lvds 125.0000 1.8 v lvds
si5334 28 preliminary rev. 0.16 ethernet/fibre channel (continued) si5334c- a00116-gm clock 25.0000 3.3 v cmos 156.2500 1.8 v lvds 156.2500 1.8 v lvds 125.0000 1.8 v lvds 125.0000 1.8 v lvds si5334c- a00117-gm xtal 25.0000 n/a 125.0000 3.3 v cmos 125.0000 3.3 v cmos 106.2500 3.3 v cmos 106.2500 3.3 v cmos si5334c- a00118-gm clock 25.0000 3.3 v cmos 125.0000 3.3 v cmos 125.0000 3.3 v cmos 106.2500 3.3 v cmos 106.2500 3.3 v cmos si5334c- a00119-gm xtal 25.0000 n/a 125.0000 1.8 v lvds 125.0000 1.8 v lvds 106.2500 3.3 v lvpecl 106.2500 3.3 v lvpecl si5334c- a00120-gm clock 25.0000 3.3 v cmos 125.0000 1.8 v lvds 125.0000 1.8 v lvds 106.2500 3.3 v lvpecl 106.2500 3.3 v lvpecl si5334b- a00121-gm xtal 25.0000 n/a 212.5000 3.3 v lvpecl 212.5000 3.3 v lvpecl 106.2500 3.3 v lvpecl 106.2500 3.3 v lvpecl si5334b- a00122-gm clock 25.0000 3.3 v cmos 212.5000 3.3 v lvpecl 212.5000 3.3 v lvpecl 106.2500 3.3 v lvpecl 106.2500 3.3 v lvpecl si5334b- a00123-gm xtal 25.0000 n/a 212.5000 3.3 v lvds 212.5000 3.3 v lvds 106.2500 3.3 v lvds 106.2500 3.3 v lvds si5334b- a00124-gm clock 25.0000 3.3 v cmos 212.5000 3.3 v lvds 212.5000 3.3 v lvds 106.2500 3.3 v lvds 106.2500 3.3 v lvds si5334c- a00125-gm xtal 25.0000 n/a 156.2500 3.3 v lvpecl 155.5200 3.3 v lvpecl 125.0000 1.8 v lvds 106.2500 3.3 v lvpecl si5334c- a00126-gm clock 25.0000 3.3 v cmos 156.2500 3.3 v lvpecl 155.5200 3.3 v lvpecl 125.0000 1.8 v lvds 106.2500 3.3 v lvpecl si5334c- a00127-gm clock 125.0000 3.3 v lvpecl 156.2500 3.3 v lvpecl 156.2500 3.3 v lvpecl 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl si5334c- a00128-gm clock 156.2500 3.3 v lvpecl 155.5200 3.3 v lvpecl 155.5200 3.3 v lvpecl 125.0000 3.3 v lvpecl 125.0000 3.3 v lvpecl table 18. si5334 standard frequency plans (continued) clkin clk0 clk1 clk2 clk3 application opn input freq format freq format freq format freq format freq format
si5334 preliminary rev. 0.16 29 synchronous ethernet (rx- side) si5334c- a00129-gm clock 19.4400 3.3 v cmos 25.0000 3.3 v cmos 25.0000 3.3 v cmos 25.0000 3.3 v cmos 25.0000 3.3 v cmos si5334c- a00130-gm clock 25.0000 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos si5334c- a00131-gm clock 125.0000 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos si5334c- a00132-gm clock 156.2500 3.3 v lvpecl 19.4400 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos si5334c- a00133-gm clock 161.1328 3.3 v lvpecl 19.4400 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos 19.4400 3.3 v cmos pdh si5334c- a00134-gm clock 19.4400 3.3 v cmos 1.5440 3.3 v cmos 1.5440 3.3 v cmos 1.5440 3.3 v cmos 1.5440 3.3 v cmos si5334c- a00135-gm clock 19.4400 3.3 v cmos 2.0480 3.3 v cmos 2.0480 3.3 v cmos 2.0480 3.3 v cmos 2.0480 3.3 v cmos si5334c- a00136-gm clock 19.4400 3.3 v cmos 2.0480 3.3 v cmos 2.0480 3.3 v cmos 1.5440 3.3 v cmos 1.5440 3.3 v cmos si5334c- a00137-gm clock 19.4400 3.3 v cmos 8.1920 3.3 v cmos 4.0960 3.3 v cmos 2.0480 3.3 v cmos 2.0480 3.3 v cmos si5334c- a00138-gm clock 19.4400 3.3 v cmos 44.7360 3.3 v cmos 44.7360 3.3 v cmos 34.3680 3.3 v cmos 34.3680 3.3 v cmos broadcast video si5334c- a00139-gm xtal 27.0000 n/a 74.2500 3.3 v cmos 74.1758 3.3 v cmos 54.0000 3.3 v cmos 27.0000 3.3 v cmos si5334c- a00140-gm clock 27.0000 3.3 v cmos 74.2500 3.3 v cmos 74.1758 3.3 v cmos 54.0000 3.3 v cmos 27.0000 3.3 v cmos si5334c- a00141-gm xtal 27.0000 n/a 74.2500 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos 27.0000 3.3 v cmos si5334c- a00142-gm clock 27.0000 3.3 v cmos 74.2500 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos 27.0000 3.3 v cmos si5334c- a00143-gm xtal 27.0000 n/a 108.0000 3.3 v lvds 74.2500 3.3 v lvds 74.1758 3.3 v lvds 54.0000 3.3 v lvds si5334c- a00144-gm clock 27.0000 3.3 v cmos 108.0000 3.3 v lvds 74.2500 3.3 v lvds 74.1758 3.3 v lvds 54.0000 3.3 v lvds table 18. si5334 standard frequency plans (continued) clkin clk0 clk1 clk2 clk3 application opn input freq format freq format freq format freq format freq format
si5334 30 preliminary rev. 0.16 broadcast video (continued) si5334c- a00145-gm xtal 27.0000 n/a 74.1758 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos si5334c- a00146-gm clock 27.0000 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos si5334c- a00147-gm xtal 27.0000 n/a 74.2500 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos si5334c- a00148-gm clock 27.0000 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos si5334c- a00149-gm xtal 27.0000 n/a 74.2500 3.3 v cmos 74.2500 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos si5334c- a00150-gm clock 27.0000 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos si5334c- a00151-gm xtal 27.0000 n/a 148.5000 3.3 v lvds 148.3516 3.3 v lvds 74.2500 3.3 v cmos 74.1758 3.3 v cmos si5334c- a00152-gm clock 27.0000 3.3 v cmos 148.5000 3.3 v lvds 148.3516 3.3 v lvds 74.2500 3.3 v cmos 74.1758 3.3 v cmos si5334c- a00153-gm xtal 27.0000 n/a 156.2500 3.3 v lvds 148.5000 3.3 v lvds 148.3516 3.3 v lvds 108.0000 3.3 v lvds si5334b- a00154-gm clock 27.0000 3.3 v cmos 156.2500 3.3 v lvds 148.5000 3.3 v lvds 148.3516 3.3 v lvds 108.0000 3.3 v lvds si5334c- a00155-gm xtal 27.0000 n/a 148.3516 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds si5334b- a00156-gm clock 27.0000 3.3 v cmos 148.3516 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds si5334c- a00157-gm xtal 27.0000 n/a 148.5000 3.3 v lvds 148.5000 3.3 v lvds 148.5000 3.3 v lvds 148.5000 3.3 v lvds si5334c- a00158-gm clock 27.0000 3.3 v cmos 148.5000 3.3 v lvds 148.5000 3.3 v lvds 148.5000 3.3 v lvds 148.5000 3.3 v lvds si5334c- a00159-gm xtal 27.0000 n/a 148.5000 3.3 v lvds 148.5000 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds si5334c- a00160-gm clock 27.0000 3.3 v cmos 148.5000 3.3 v lvds 148.5000 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds table 18. si5334 standard frequency plans (continued) clkin clk0 clk1 clk2 clk3 application opn input freq format fre q format freq format freq format freq format
si5334 preliminary rev. 0.16 31 broadcast video (continued) si5334c- a00161-gm clock 74.1758 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos 74.2500 3.3 v cmos si5334c- a00162-gm clock 74.2500 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos 74.1758 3.3 v cmos si5334c- a00163-gm clock 148.3516 3.3 v lvds 148.5000 3.3 v lvds 148.5000 3.3 v lvds 148.5000 3.3 v lvds 148.5000 3.3 v lvds si5334b- a00164-gm clock 148.3516 3.3 v lvds 270.0000 3.3 v lvds 270.0000 3.3 v lvds 270.0000 3.3 v lvds 270.0000 3.3 v lvds si5334c- a00165-gm clock 148.5000 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds 148.3516 3.3 v lvds si5334b- a00166-gm clock 148.5000 3.3 v lvds 270.0000 3.3 v lvds 270.0000 3.3 v lvds 270.0000 3.3 v lvds 270.0000 3.3 v lvds pcie* si5334m- a00167-gm xtal 25.0000 n/a 100.0000 3.3 v hcsl 100.0000 3.3 v hcsl 100.0000 3.3 v hcsl 100.0000 3.3 v hcsl si5334m- a00168-gm clock 25.0000 3.3 v cmos 100.0000 3.3 v hcsl 100.0000 3.3 v hcsl 100.0000 3.3 v hcsl 100.0000 3.3 v hcsl notes: 1. ?0.5% downspread enabled on clk0-clk3 2. to request new frequency plans/device configurations, plea se contact your local silicon labs sales representative. table 18. si5334 standard frequency plans (continued) clkin clk0 clk1 clk2 clk3 application opn input freq format fre q format freq format freq format freq format
si5334 32 preliminary rev. 0.16 d ocument c hange l ist revision 0.1 to revision 0.15 ? updated tables for ac/dc specs to remove tbds. ? updated ordering opn in table 10 from 34c to 34m-00167/00168-gm. ? updated ssc information for correct part number. ? removed diagram in section 3. ? corrected pin 12 description ? removed low-power lvpecl mode. ? updated pin descriptions to say 710 mhz. ? added pcb layout notes on via requirements for gnd pad. ? removed description of field programming as this is not supported. revision 0.15 to revision 0.16 ? changed cycle-cycle jitter spec from pk-pk to pk. ? change refclk1 pin name to refclkse.
si5334 preliminary rev. 0.16 33 n otes :
si5334 34 preliminary rev. 0.16 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. a dditionally, silicon laboratorie s assumes no responsibility for the functioning of und escribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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